1. Field of the Invention
The present invention relates to a charge pump device and driving capability adjustment method thereof, and more particularly, to a charge pump device and driving capability adjustment method thereof capable of adjusting an output driving capability according to loading status while balancing both output ripple and loading affording capability.
2. Description of the Prior Art
Generally speaking, a charge pump device can be utilized for providing a stable output voltage to different loadings. In the prior art, the charge pump device is controlled by an operational amplifier or by a comparator. Under the structure utilizing the operational amplifier for performing controlling, the output voltage has smaller output ripples but may be unstable under different loadings and different external components. Although the output voltage is stable under the structure utilizing the comparator for controlling, the output voltage has greater periodic output ripples and may have noise in audio frequency band under certain loadings.
For example, please refer to FIG. 1A, which is a schematic diagram of a conventional charge pump device 10. The charge pump device 10 is realized in the structure utilizing the operational amplifier for performing controlling, and comprises a charge pump circuit 102, an operation amplifier 104, an adjusting transistor 106 and a driving stage 108. In brief, the charge pump circuit 102 generates an output voltage VGH according to a driving signal DRVP generated by the driving stage 108. For example, the charge pump circuit 102 may be a Dickson charge pump which controls an input voltage AVDD to charge flying capacitors CF1 and CF2 when the driving signal DRVP is at a low logic level, such that the charges stored in the flying capacitor CF1 and CF2 are outputted to an output capacitor CS1 when the driving signal DRVP is at a high logic level for sharing charge of the flying capacitor CF1 and CF2, to pump the output voltage VGH to a desired voltage level.
As to generating the driving signal DRVP for performing controlling, the voltage dividing resistors R1 and R2 divide the output voltage VGH for generating a feedback voltage FBP to the operational amplifier 104. The operational amplifier 104 compares the feedback voltage FBP and a reference voltage VREF to provide an output signal OP_OUT to the adjusting transistor 106 for performing adjusting the driving capability. Specifically, the feedback voltage FBP becomes higher and the output signal OP_OUT is also pulled high when the output voltage VGH becomes higher, such that the conducting resistance of the adjusting transistor 106 becomes greater (i.e. the gate-source voltage of the adjusting transistor 106 becomes smaller); and the feedback voltage FBP becomes lower and the output signal OP_OUT is pulled low when the output voltage VGH becomes lower, such that the conducting resistance of the adjusting transistor 106 becomes smaller (i.e. the gate-source voltage of the adjusting transistor 106 becomes smaller). Next, the driving stage 108 generates the driving signal DRVP according to the adjusting transistor 106 and a clock signal CLK, for controlling the charge pump circuit 102 to generate the desired output voltage VGH.
In detail, please refer to FIG. 1B, which is a waveform diagram of related signals of charge pump device 10 shown in FIG. 1A. As shown in FIG. 1B, since the driving stage 108 continuously triggers the driving signal DRVP to a high logic level when the clock signal CLK is at a high logic level and the conducting resistance of the adjusting transistor 106 is adjusted according to the output voltage VGH, a smaller charging current of the charge pump circuit 102 generated to the output voltage VGH of the output capacitor CS1 is obtained. Since the ripples of the output voltage VGH are proportional to the charging current, the output voltage VGH therefore has smaller output ripples.
However, since the output of the charge pump device 10 has a pole equals 1/(2π×CS1×loading resistance), the pole varies due to different external loadings and different capacitances of output capacitor CS1, causing the charge pump 10 to be unstable under certain circumstances.
On the other hand, please refer to FIG. 2A, which is a schematic diagram of another conventional charge pump device 20. The charge pump device 20 is partially similar to the charge pump device 10, and thus the same symbols are used for components and signals with the similar functions. The charge pump device 20 is controlled by a comparator, and comprises a charge pump circuit 102, a comparing circuit 204, a driving stage 206 and voltage dividing resistors R1 and R2, wherein the comparing circuit 204 comprises a comparator 208, a flip-flop 210 and a NAND gate 212. The operations of the charge pump device 102 pumps the output voltage VGH to the desired level according to the driving signal DRVP generated the driving stage 206 can be referred to the above, and are not narrated herein for brevity.
As to generation of the driving signal DRVP for performing controlling, the voltage dividing resistors R1 and R2 divide the output voltage VGH for generating the feedback voltage FBP to the comparator 208. The comparator 208 compares the feedback voltage FBP and the reference voltage VREF for providing a comparing output signal COMP_OUT, and the flip-flop 210 samples the voltage level of the comparing output signal COMP_OUT at the rising edges of the clock signal CLK and provides a comparing sample signal COMP_SAM (i.e. different from the comparing output signal COMP_OUT which may vary due to noise or interference, the comparing sample signal COMP_SAM stays at the same level during a time period of the clock signal CLK). The NAND gate 212 generates a comparing result signal COMP_SIG to the driving stage 206, such that the driving stage 206 can accordingly generate the toggling signal DRVP for controlling the charge pump circuit 102 to generate the desired output voltage VGH.
In detail, please refer to FIG. 2B, which is a waveform diagram of related signals of the charge pump device 20 shown in FIG. 2A. As shown in FIG. 2B, when the output voltage VGH is lower than a target voltage (i.e. the feedback voltage FBP is smaller than the reference voltage VREF), the comparing sample signal COMP_SAM starts outputting a high logic level for a period starting at a rising edge of the clock signal CLK. When both the comparing sample signal COMP_SAM and the clock signal CLK are at the high logic level (i.e. the comparing result signal COMP_SIG is at the low logic level), the driving signal DRVP is at the high logic level for controlling the charge pump circuit 102 to continuously charge the output voltage VGH. Next, after the output voltage VGH becomes greater than the target voltage, the comparing sample signal COMP_SAM outputs a low logic level for a period starting at another rising edge of the clock signal CLK, to keep the driving signal DRVP at the low logic level for controlling the charge pump device 102 not to charge the output voltage VGH. The output voltage VGH of the output capacitor CS1 is gradually decreased in driving the external loading. The above operations proceed repeatedly until the output voltage VGH is lower than the target voltage. In such a condition, since the charge pump device 20 only compares the feedback voltage FBP and the reference voltage VREF, the output voltage VGH is stable under different loading and capacitor CS1 conditions.
On the other hand, in comparison with the charge pump device 10 triggering the driving signal DRVP to the high logic level when the clock signal CLK is at the high logic level, the charge pump device 20 triggers the driving signal DRVP to high logic level only when both the comparing sample signal COMP_SAM and the clock signal CLK are at the high logic level (the driving signal DRVP is selectively triggered), such that a larger charging current of the charge pump circuit 102 is obtained, leading to larger output ripples.
In detail, the level of the high logic level of the driving signal DRVP relates to the driving capability corresponding to the driving signal DRVP. In the structure of comparator, since the transistors of driving stage 206 are turned fully on, the level of the driving signal DRVP is higher when the driving signal is at the high logic level. On the contrary, in the structure of the operational amplifier, since the output signal OP_OUT of the operational amplifier 104 adjusts the driving capability of the driving stage 108 via adjusting the transistor 106, the level of the driving signal DRVP is lower when the driving signal DRVP is at the high logic level. The driving capability provided by the charge pump circuit 102 is determined by the number of times the driving signal DRVP is triggered to the high logic level and the amplitude of the driving signal DRVP. For different loadings, the comparator structure adjusts the number of times the driving signal DRVP is triggered to the high logic level, while the operational amplifier structure adjusts the amplitude of the driving signal DRVP when the driving signal DRVP is at the high logic level.
When the system is stable, the average charging current of the charge pump circuit 102 for charging the output voltage VGH must equal the loading current, such that the output voltage VGH can be kept at the target level. For the same the loading current, since the driving signal DRVP in the operational amplifier structure keeps toggling while the one in the comparator structure toggles periodically, the charging current of the charge pump circuit 102 in the comparator structure is larger than that in the operational amplifier structure. Furthermore, the output ripples are proportional to the charging current, so the output voltage VGH of the comparator structure therefore has greater periodic output ripples. Thus, the comparator structure may generate audio noise which can be heard by human ear (20 Hz-20 kHz) under certain external loadings.
For example, please refer to FIG. 3, which is a waveform diagram of the driving signal DRVP shown in FIG. 2 generates audio noise under certain loadings. As shown in FIG. 3, when the driving signal DRVP continually toggles (i.e. a burst) for increasing the output voltage VGH to the target voltage, although the frequency of the driving signal continuously triggering (i.e. the frequency of the clock signal CLK) is higher than 20 kHz, the interval between two times of the driving signal DRVP continually triggering (i.e. the ripple frequency of the output voltage VGH) may be within 20 Hz-20 kHz, such that the audio noise is generated.
Therefore, although the charge pump device 20 controlled by the comparator does not cause problem of stability, the charge pump device 20 has greater output ripple which results in the audio noise under certain external loadings.